Dynamic Instruction Reuse. This scheme implements reuse based upon Operand Values (Sv) . Designed an associative reuse buffer (2 level) and dynamic cache coherency protocol. To obtain best results and performance using this scheme, FIFO replacement policy was used.
Results : 1. The IPC boost ranges from 14 to 31 %
2. Addition of an associative reuse buffer showed significant
increase in the IPC.
3. Designed and developed dynamic cache coherency protocol to
enhance the
existing reuse Instruction scheme.
4. Shows that Sv scheme is cost effective in terms of the
amount hardware
required for the design.
Design and Implementation of the Decoder Logic of
the PCS sub layer of the 10GB Ethernet (IEEE 802.3ae) :The
primary goal of the project is to implement the decoder logic of the Physical
Coding Sub layer (PCS) of the 10Gigabit Ethernet. Was responsible for
implementing the three key state machines Receive State Machine, Lock State
Machine and BER State machine; was also responsible for the 64B/66B decoder
block. Timing Optimization was done using Leonardo .
Results: 1. All the state machines were designed
according to the
specifications.
2. 64B/66B decoder block was designed.
3. Timing Optimization was done on all the blocks.
Design of RDRAM memory controller : Design of a Direct RAMBUS (RDRAM) memory controller for PIII processor with an AGP interface for a 133 MHz clock. The memory controller was modeled and simulated in VHDL and synthesized as a custom ASIC.
Results: 1. RDRAM Memory Controller was designed
and synthesized.
2. Clock Synchronization was done by designing a gear block.
3. Integrated successfully with AGP and Host Bus interface.
4. Custom ASIC was developed successfully.
Design and Analysis of a Bandgap Reference using
Bi-Polar technology : The bandgap reference circuit is as a temperature
independent circuit. When self-biasing technique is used; the power supply
sensitivity can be reduced. The main design criteria for this project was to
achieve an total power dissipation less than 10mW and PSRR above than 60dB and
total output resistance less than 1ohm and a zero temperature coefficient at
300K.
Results: 1. Total power dissipation of less than 10mW was achieved.
2. PSRR of 67dB was achieved.
3. The zero temperature co-efficient was found exactly at 300K.
4. Total output resistance of 0.2 ohms was achieved.
Design and Layout of Encryption and Decryption of
stream ciphers : This project focused on the design , verification and
layout of a stream ciphers. The design was implemented using VHDL and Leonardo
Spectrum was used to synthesize the design to RTL Level. Schematics was
generated from EDIF, layout was done using auto placement and routing tools.
Results: 1. Encryption and Decryption blocks were successfully designed
and synthesized
2. DRC and LVS were done successfully. Floor planning , P&R
and I/O pad
placement was done successfully.
3. Custom IC Layout was done till the Mask Level.
Cross Talk immune VLSI design using a network of PLA’s
embedded in a regular layout fabric :
This project involves implementing the logic nettles in the form of network
of medium sized PLA’s to reduce cross talk. This results in extremely fast and
dense circuits. (This project was based on
the project done by Sunil P. Khatri Colorado state
university and {Alberto Sangiovanni-Vincentelli , Robert K. Brayton } from
UC Berkley ).
Results: 1. Timing improvement of 12-15 % was
observed
2. Signal Integrity problems were eliminated.
Socket Programming using “JAVA†:The project is
based on client-server technology, uses Server sockets and client sockets to
facilitate transmission of data on the TCP/IP domain between the client and
server. The server handles multiple clients using the multiple threads.
Results: 1. Server sockets and client sockets were successfully developed
and tested.
2. Can handle multiple clients