About the Author
Kiran Bulusu is a Strategic Account Management professional in Electronics Design Automation (EDA)/Semiconductor Industry.
He has experience in Product Positioning,Revenue Generation, building customer relationships and converting them into strategic accounts. His strategies and technical competence helped win many aggressive pre-sales campaigns in EDA and Semiconductor industry.
His technical experience is primarily starting from logic synthesis to GDSII including DFT/Formal Verification/Hierarchical Floorplanning on various process all the way from 0.13u to 32nm . He has worked ASIC designs implementation on couple of high performance processors from ARM (Cortex A9/15)/MIPS (74K,1004K,1024K) /Sun (OpenSparc T2 ) and Graphics Cores (SGX) from Imagination Technologies , UK .
His other interests include Management Consulting,Marketing and Entrepreneurship. He is currently employed at Cadence Design Systems.
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Tag Archives: top down flow
OpenSparc-T2 Synthesis -Part 2 ( Top level Synthesis )
OK as promised earlier, here are the part2 top level synthesis -cpu module I’m assuming that the block level synthesis using bottom-up flow is done using part-1 and all Glassboxes (Magma’s Terminology for abstracts which are BTW efficient that ILM’s etc and are very suitable for implementing multi-million instances designs) are generated.
Click to continue reading “OpenSparc-T2 Synthesis -Part 2 ( Top level Synthesis )”
