About the Author
Kiran Bulusu is a Strategic Account Management professional in Electronics Design Automation (EDA)/Semiconductor Industry.
He has experience in Product Positioning,Revenue Generation, building customer relationships and converting them into strategic accounts. His strategies and technical competence helped win many aggressive pre-sales campaigns in EDA and Semiconductor industry.
His technical experience is primarily starting from logic synthesis to GDSII including DFT/Formal Verification/Hierarchical Floorplanning on various process all the way from 0.13u to 32nm . He has worked ASIC designs implementation on couple of high performance processors from ARM (Cortex A9/15)/MIPS (74K,1004K,1024K) /Sun (OpenSparc T2 ) and Graphics Cores (SGX) from Imagination Technologies , UK .
His other interests include Management Consulting,Marketing and Entrepreneurship. He is currently employed at Cadence Design Systems.
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Tag Archives: opensparct2
OpenSparc-T2 Synthesis -Part 2 ( Top level Synthesis )
OK as promised earlier, here are the part2 top level synthesis -cpu module I’m assuming that the block level synthesis using bottom-up flow is done using part-1 and all Glassboxes (Magma’s Terminology for abstracts which are BTW efficient that ILM’s etc and are very suitable for implementing multi-million instances designs) are generated.
Click to continue reading “OpenSparc-T2 Synthesis -Part 2 ( Top level Synthesis )”
OpenSparc-T2 Synthesis -Part 3 ( Hierarchical Floorplan Creation/Refining )
This is continuation of Posts 1 and 2 which adress the block level synthesis and top level synthesis of the opensparct2 processor . This post concentrates on building the floorplan/SDC etc suitable for block level P&R implementation. Due to short of time and bandwidth, I couldnt get a chance to build the floorplan for full chip “cpu” module, but to keep the momentum going and for enthusiasts, I built the flow for the “rtx” module which is quite big ( around 7M+ instances ) below and can act as good testcase to build the reference flow. Anyone who has the full cpu fix-time-final volcano from your top level synthesis run, can load it in place rtx or alternatively import the full chip netlist and follow the rest of the flow.
Folks can re-use the P&R implementation script for block level from my Nova Processor Core RTL-GDSII post .
We are using channel style and the script below basically does the following :
OpenSparc-T2 Synthesis -Part 1
For anyone interested in learning processor architectures and synthesizing processor cores, they can refer to www.opensparc.net . Sun Micro has donated its entire sparc processor core to Opensource. They even provide scripts for Synthesis using Synopsys DC and for Verification as well.
Due to my previous back ground and interest in Processor Architectures, given my current CAD background, I was very curious to learn and synthesize these cores. Also, the synthesis scripts are for to use with TALUS platform from Magma. The scripts will do the bottom-up synthesis & top level synthesis, Scan Insertion, Timing Optimization and will write a sized netlist .
Please note that, these scripts are not meant to use for any commerical purposes and strictly for personal/learning purposes only and provided “as-is” . Neither the scripts I provided below nor the work is endorsed and has nothing to do with my employer . Additionally please make sure you read all the disclaimers/license agreements when you download the cores.
Due to short of bandwidth and resources in mind, I’m only publishing logic synthesis scripts. May be time permitting, I will publish the P&R scripts in Part 2 series.
OpenSparc-T2 has the following features and this runs at 1.4GHz (714ps clock period )
8 Sparc cores, 8 threads each
Shared 4MB L2, 8-banks, 16-way associative
Two 10/1 Gb Enet ports w/onboard packet classification and filtering
One PCI-E x8 1.0 port
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Main modules in the design are :
CCX – Crossbar
CCU – Clock control
DMU/PEU – PCI Express
EFU – Efuse (redundancy)
ESR – Ethernet SERDES
FSR – FBDIMM SERDES
L2B – L2 write-back buffers
L2D – L2 Data L2D – L2 Data
L2T – L2 tags
MCU – Memory controller
MIO – Miscellaneous I/O
PSR – PCI-Express SERDES
RDP/TDS/RTX/MAC – Ethernet
SII/SIO – I/O datapath in/out to memory
SPC – Sparc core
TCU – Test control unit
PCI-E is not provided with the binary when you download and its a seperate IP.
cpu is the top level module name .
The following source browser might help everyone when navigating through the hierarchy and for understanding RTL .
