Tag: Logic Synthesis
Questions to ask before you consider “yet another synthesis tool”..
by kiran on Sep.18, 2009, under EDA, General, Management
You need to know the exact criteria why you are considering other tools else its waste of time for you/your team and for vendor as well. Some common pain points are
A.QOR (Quality of Results)
B.Turn Around Time (TAT ) and Stability of the tool
C.Reactive mode type of Support from Vendor/Poor Support/Long resolution to issues
D.Interoperability with other tools
E.Cost of licenses itself.
Click to continue reading “Questions to ask before you consider “yet another synthesis tool”..”
OpenSparc-T2 Synthesis -Part 2 ( Top level Synthesis )
by kiran on Jun.08, 2009, under EDA
OK as promised earlier, here are the part2 top level synthesis -cpu module I’m assuming that the block level synthesis using bottom-up flow is done using part-1 and all Glassboxes (Magma’s Terminology for abstracts which are BTW efficient that ILM’s etc and are very suitable for implementing multi-million instances designs) are generated.
Click to continue reading “OpenSparc-T2 Synthesis -Part 2 ( Top level Synthesis )”
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- Questions to ask before you consider “yet another synthesis tool”.. September 18, 2009
- Semiconductor value chain…Its in the system stupid… September 18, 2009
- OpenSparc-T2 Synthesis-Part 4 (Block Level Impl till GDSII) June 9, 2009
- OpenSparc-T2 Synthesis -Part 2 ( Top level Synthesis ) June 9, 2009
- OpenSparc-T2 Synthesis -Part 3 ( Hierarchical Floorplan Creation/Refining ) June 9, 2009
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