About the Author
Kiran Bulusu is a Strategic Account Management professional in Electronics Design Automation (EDA)/Semiconductor Industry.
He has experience in Product Positioning,Revenue Generation, building customer relationships and converting them into strategic accounts. His strategies and technical competence helped win many aggressive pre-sales campaigns in EDA and Semiconductor industry.
His technical experience is primarily starting from logic synthesis to GDSII including DFT/Formal Verification/Hierarchical Floorplanning on various process all the way from 0.13u to 32nm . He has worked ASIC designs implementation on couple of high performance processors from ARM (Cortex A9/15)/MIPS (74K,1004K,1024K) /Sun (OpenSparc T2 ) and Graphics Cores (SGX) from Imagination Technologies , UK .
His other interests include Management Consulting,Marketing and Entrepreneurship. He is currently employed at Cadence Design Systems.
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Tag Archives: incremental synthesis
Questions to ask before you consider “yet another synthesis tool”..
You need to know the exact criteria why you are considering other tools else its waste of time for you/your team and for vendor as well. Some common pain points are
A.QOR (Quality of Results)
B.Turn Around Time (TAT ) and Stability of the tool
C.Reactive mode type of Support from Vendor/Poor Support/Long resolution to issues
D.Interoperability with other tools
E.Cost of licenses itself.
Click to continue reading “Questions to ask before you consider “yet another synthesis tool”..”
Posted in EDA, General, Management
Tagged chip development cycle time, correlation, EDA support, incremental synthesis, interoperability, Logic Synthesis, low powe, physical design tool correlation, QOR metrics, synthesis evaluation, Synthesis ROI, Synthesis tools, tool interoperability
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