About the Author
Kiran Bulusu is a Strategic Account Management professional in Electronics Design Automation (EDA)/Semiconductor Industry.
He has experience in Product Positioning,Revenue Generation, building customer relationships and converting them into strategic accounts. His strategies and technical competence helped win many aggressive pre-sales campaigns in EDA and Semiconductor industry.
His technical experience is primarily starting from logic synthesis to GDSII including DFT/Formal Verification/Hierarchical Floorplanning on various process all the way from 0.13u to 32nm . He has worked ASIC designs implementation on couple of high performance processors from ARM (Cortex A9/15)/MIPS (74K,1004K,1024K) /Sun (OpenSparc T2 ) and Graphics Cores (SGX) from Imagination Technologies , UK .
His other interests include Management Consulting,Marketing and Entrepreneurship. He is currently employed at Cadence Design Systems.
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OpenSparc-T2 Synthesis -Part 3 ( Hierarchical Floorplan Creation/Refining )
This is continuation of Posts 1 and 2 which adress the block level synthesis and top level synthesis of the opensparct2 processor . This post concentrates on building the floorplan/SDC etc suitable for block level P&R implementation. Due to short of time and bandwidth, I couldnt get a chance to build the floorplan for full chip “cpu” module, but to keep the momentum going and for enthusiasts, I built the flow for the “rtx” module which is quite big ( around 7M+ instances ) below and can act as good testcase to build the reference flow. Anyone who has the full cpu fix-time-final volcano from your top level synthesis run, can load it in place rtx or alternatively import the full chip netlist and follow the rest of the flow.
Folks can re-use the P&R implementation script for block level from my Nova Processor Core RTL-GDSII post .
We are using channel style and the script below basically does the following :
