About the Author
Kiran Bulusu is a Strategic Account Management professional in Electronics Design Automation (EDA)/Semiconductor Industry.
He has experience in Product Positioning,Revenue Generation, building customer relationships and converting them into strategic accounts. His strategies and technical competence helped win many aggressive pre-sales campaigns in EDA and Semiconductor industry.
His technical experience is primarily starting from logic synthesis to GDSII including DFT/Formal Verification/Hierarchical Floorplanning on various process all the way from 0.13u to 32nm . He has worked ASIC designs implementation on couple of high performance processors from ARM (Cortex A9/15)/MIPS (74K,1004K,1024K) /Sun (OpenSparc T2 ) and Graphics Cores (SGX) from Imagination Technologies , UK .
His other interests include Management Consulting,Marketing and Entrepreneurship. He is currently employed at Cadence Design Systems.
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Tag Archives: Bk Level P&R
OpenSparc-T2 Synthesis-Part 4 (Block Level Impl till GDSII)
This is final and last part of the Open Sparc T2 processor synthesis series. Actually, I wont be posting anything new here, but just for completeness sake of the series, I’m creating a new post. Sorry about this, but I dont see any point in reposting the same thing twice.
The P&R script for block level implementation can be picked from my earlier post Nova H.264 decoder core P&R script
Click to continue reading “OpenSparc-T2 Synthesis-Part 4 (Block Level Impl till GDSII)”
Posted in EDA
Tagged Bk Level P&R, Congestion, Floorplan, GDSII, Hydra, Magma, magma design automation, Routing, Talus, Talus Design, Vortex
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