Kiran Bulusu’s Blog

Normally, I dont post job ads , so this  is one time exception (hopefully!!)

My current company Magma Design Automation is hiring and looking for a person to fill in the Field Applications Engineer role..Qualifications would include : BS/MS in EE or related disciplines, Anyone with 3-5yrs experience in VLSI/ASIC Backend (physical synthesis/low power/ Multi-Mode & Multi Corner/ECO flows) , Strong with TCL scripting;Experience with Magma Tools in the past would be a plus. BTW, the location would be San Jose, California,US.  You might be asked to come for in person interview at your own expense.

If you are interested, please send me your resume your kbulusu at gmail dot com

You need to know the exact criteria why you are considering other tools else its waste of time for you/your team and for vendor as well. Some common pain points are
A.QOR (Quality of Results)
B.Turn Around Time (TAT ) and Stability of the tool
C.Reactive mode type of Support from Vendor/Poor Support/Long resolution to issues
D.Interoperability with other tools
E.Cost of licenses itself.

This is final and last part of the Open Sparc T2 processor synthesis series. Actually, I wont be posting anything new here, but just for completeness sake of the series, I’m creating a new post.  Sorry about this, but I dont see any point in reposting the same thing twice.

The P&R script for block level implementation can be picked from my earlier post Nova H.264 decoder core P&R script

OK as promised earlier, here are the part2 top level synthesis -cpu module I’m assuming that the block level synthesis using bottom-up flow is done using part-1 and all Glassboxes (Magma’s Terminology for abstracts which are BTW efficient that ILM’s etc and are very suitable for implementing multi-million instances designs) are generated.

This is continuation of Posts 1 and 2 which adress the block level synthesis and top level synthesis of the opensparct2 processor . This post concentrates on building the floorplan/SDC etc suitable for block level P&R implementation. Due to short of time and bandwidth, I couldnt get a chance to build the floorplan for full chip “cpu” module, but to keep the momentum going and for enthusiasts, I built the flow for the “rtx” module which is quite big ( around 7M+ instances ) below and can act as good testcase to build the reference flow. Anyone who has the full cpu fix-time-final volcano from your top level synthesis run, can load it in place rtx or alternatively import the full chip netlist and follow the rest of the flow.

Folks can re-use the P&R implementation script for block level  from my Nova Processor Core RTL-GDSII post .

We are using channel style and the script below basically does the following :