Kiran Bulusu’s Blog

You need to know the exact criteria why you are considering other tools else its waste of time for you/your team and for vendor as well. Some common pain points are
A.QOR (Quality of Results)
B.Turn Around Time (TAT ) and Stability of the tool
C.Reactive mode type of Support from Vendor/Poor Support/Long resolution to issues
D.Interoperability with other tools
E.Cost of licenses itself.

Other questions to dig further are :

1.Does it enable your RTL designers to experiment with multiple architectures in the same..say 2-3 iterations a day ..fix any major outliers in RTL/timing constraints etc.
2.How does it correlate with your Physical Design tools? There is no good soln out there, but vendors are coming up with lot of creative ways to close this gap as much as possible..
3. If TAT is key, dont measure it merely based on 1-2 blocks …measure it on the whole chip development cycle..(incremental synthesis might add value here ) ..how much does it save on complete chip development cycle..thats the real ROI you will have or save by switching…you simply doesnt want to switch for marginal improvements like 0.5x or 1.5x ..atleast 4-5x speedup probably might be a rule of thumb and only then you can save some real TAT…
4.Does it fit in your existing tool eco system? If not, how much more work is necessary?
5.Any interoperability issues? Like if your Synthesis and DFT vendors are different.
6.Does it support incremental synthesis? Not like an ECO, but if your design “top” has 2 modules A and B, can you just recompile A without elaborating B again.
7.If you are using any arithmetic IPs be it designware or from 3rd party tools, does it support?
8.If you are having legacy RTL with pragma’s etc, does it support?

9.If you are operating in a consumer electronics market segment, you might have multiple modes and multiple PVT corners/ may be low power strategies, does it support?
10. If low power chips, can the power intent be expressed in both UPF/CPF formats . If your power verification tool and synthesis support diff formats, you are in a fix!!
11.If your design is or integrates high perf cores , can the synthesis tool handle and deliver it with good TAT?
12. There is no direct way to measure, but how good the tool is with Datapath  & Control logic synthesis. How does it do if its a crossbar or high interconnect chips. Your correlation might be way off with PD tools.

13. Measure QOR metrics like WNS/TNS/Failing endpoints for timing, Cell Cnt/Flop Cnt/Wirelength/Util for area if reason for switching is pure QOR based.
14.How much time you need to spend on the design methodology/flow development once you bought. If its couple of weeks to months, is it worth? How many chips are you planning to TO with this newly developed flow etc. If its a reasonable number, then it might be else for 1 or 2 chips, may the ROI doesnt justify.