About the Author
Kiran Bulusu is a Strategic Account Management professional in Electronics Design Automation (EDA)/Semiconductor Industry.
He has experience in Product Positioning,Revenue Generation, building customer relationships and converting them into strategic accounts. His strategies and technical competence helped win many aggressive pre-sales campaigns in EDA and Semiconductor industry.
His technical experience is primarily starting from logic synthesis to GDSII including DFT/Formal Verification/Hierarchical Floorplanning on various process all the way from 0.13u to 32nm . He has worked ASIC designs implementation on couple of high performance processors from ARM (Cortex A9/15)/MIPS (74K,1004K,1024K) /Sun (OpenSparc T2 ) and Graphics Cores (SGX) from Imagination Technologies , UK .
His other interests include Management Consulting,Marketing and Entrepreneurship. He is currently employed at Cadence Design Systems.
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Monthly Archives: October 2008
Synthesis and Implementaion (P&R) of low-power realtime H.264/AVC baseline decoder
As the title says, anyone interested in Video decoder of H.264 can check the Verilog code from Open Cores. Many kudos to the author for giving the detailed spec . There are few cores which has decent feature set
and this is one of them. For details and features , please visit the OpenCores/Authors webpage at :
http://www.opencores.org/projects.cgi/web/nova/overview
Apart from reusing the valuable cores as IP, open cores is also a valuable resource for someone willing to learn different aspects of the design from RTL-GDSII .
Design Stats & snapshots
Full Chip Layout
Clock-Tree
Congestion
Pin and Cell Density
Technology Node: 45nm process
Posted in EDA
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