Archive for October, 2008
Synthesis and Implementaion (P&R) of low-power realtime H.264/AVC baseline decoder
by kiran on Oct.23, 2008, under EDA
As the title says, anyone interested in Video decoder of H.264 can check the Verilog code from Open Cores. Many kudos to the author for giving the detailed spec . There are few cores which has decent feature set
and this is one of them. For details and features , please visit the OpenCores/Authors webpage at :
http://www.opencores.org/projects.cgi/web/nova/overview
Apart from reusing the valuable cores as IP, open cores is also a valuable resource for someone willing to learn different aspects of the design from RTL-GDSII .
Design Stats & snapshots
Full Chip Layout
Clock-Tree
Congestion
Pin and Cell Density
Technology Node: 45nm process






