Comments on: Debugging Logic Synthesis & Timing Optimization QOR issues
http://www.srikiran.net/blog/2007/09/17/debugging-qor-issue-logic-synthesis-timing-optimization/
Kiran Bulusu is an Field Applications Engineer with experience in the domain of Formal Verification, Logic Synthesis, DFT,Timing Closure, Floorplan and Place and Route, ,RTL-GDSII Design Methodology and Flow development,Pre-Sales and Post-Sales of the product. He is an evangelist and has expereince in technical marketing in EDA and Semiconductor industry. He is currently employed at Magma Design Automation.Thu, 20 Nov 2008 21:16:18 +0000http://wordpress.org/?v=2.6.2
