I have been hearing about the design/IP reuse from time to time. Today there was an article on EE times which can read by clicking this link Design-Reuse
I think many big companies have adopted the reuse methodology and realize the benefits of it. Even small-medium companies re-use the blocks or IP’s in most of their chips. So, I dont think there is any need to keep repeating the importance over and over again. Most of the companies cut down their design cycle time and costs using this reuse methodology. I think now one should look forward and see if they can get good prototyping flow . I recently worked on prototyping efforts and it correlated very well with 90nm , 130nm and 180nm. For 65nm and below, special considerations have to be adopted like taking the account of parasitic effects . With this flow, the time to achieve timing closure is significantly smaller as designer gets early feedback.
I would appreciate if anyone has any experience in developing/using the prototyping flow and can share their concerns. It will be very informative and good discussion.
